Job Summary

Locations:

Other India (Austin Texas)

Nationality:

India

Experience:

6 – 11 years

Keywords / Skills :

Skills:Microarchitecture design experience of GPU or CPU blocks within a relevant sub-system (Shader core, Texture unit, Memory system, Load/Store, etc.)High-level Verilog / System Verilog coding skill for quality RTLProgramming skills using scripting languages (Perl, Python, or other), and C/C++Familiarity using Synopsys or Cadence synthesis and clock gating methodologies.Good understanding of RTL verification flow and environments (UVM/OVM, hardware modeling, assertions and formal/semi-formal verification)Good written/verbal communication skills, strong team workMotivated, self-directed and able to work effectively, both independently and in a team.Optional Requirements ("would like to have" characteristics)1. Background in computer graphics with familiarity with overall graphics pipeline2. Design experience with synthesis and timing closure3. Back-end place-&-route experience

Function:

Manufacturing/ Engineering/ R&D

Role:

Design Manager/ Engineer

Industry:

• Power/Energy
• IT/ Computers – Hardware

Summary:

Posted On:

8th May 2016

Job Ref code:

rtl-design-engineer

The successful candidate shall work on System Verilog RTL development of power-efficient mobile graphic processors. Specifically we are seeking someone to integrate and coordinate a number of intricate sub-blocks in the graphics subsystem of a low-power Graphics Processing
Unit. As this engineer, you will work closely with the architecture team and
Contribute to the micro-architecture specifications of the shader or fixed-function subsystems Graphic Processor Unit blocks by close interaction with architects and verification engineers.
Generate high quality RTL, which is well documented, structural, synthesis-friendly, and power-efficient.
Coordinate the bring-up of complex interactions among the various sub-blocks.
Assist the power and performance team in both measuring the design’s QoR and also in working to improve these metrics.
Debug, repair, and verify logic issues and bugs (both in RTL and gate-level netlists)
Act as the liaison for the physical side of the design, collaborating with the CAD engineers regarding the floor planning and P&R of the shader sub-system.:

Skills:Microarchitecture design experience of GPU or CPU blocks within a relevant sub-system (Shader coreTexture unitMemory systemLoad/Storeetc.)High-level Verilog / System Verilog coding skill for quality RTLProgramming skills using scripting languages (PerlPythonor other)and C/C++Familiarity using Synopsys or Cadence synthesis and clock gating methodologies.Good understanding of RTL verification flow and environments (UVM/OVMhardware modelingassertions and formal/semi-formal verification)Good written/verbal communication skillsstrong team workMotivatedself-directed and able to work effectivelyboth independently and in a team.Optional Requirements (would like to have characteristics)1. Background in computer graphics with familiarity with overall graphics pipeline2. Design experience with synthesis and timing closure3. Back-end place-&-route experience

ValeurHR E-Solutions Private Limited

To see all related Jobs. Please CLICK HERE

RTL Design Engineer

PlacementFloor.com

PlacementFloor.com is a job portal for the upcoming and latest job opening in almost every sectors. The website automatically picks the recent openings and list them on priority.

Follow @ Twitter | Facebook | Google Plus

Tags: engineering / manufacturing / R&D / research

RTL Design Engineer Tuesday, 10 May 2016 No Comment